IBM sub 1 nanometer silicon transistor process achieves 7 angstrom scale using Nanostack 3D architecture for massive performance and artificial intelligence efficiency
IBM has made the world's first sub 1 nanometer silicon transistor process, achieving a physical dimension of 0.7 nanometers (or 7 angstroms). As stated by the official IBM research paper, this innovation circumvents the physical boundaries of two dimensional silicon scaling by employing a 3D transistor architecture which they term Nanostack. IBM predicts this structural change would be implemented into commercial manufacturing stands within 5 years.
Moving to 7 Angstrom nodes enables huge improvements in efficiency compared to previous generation hardware. In lab testing, processing performance has increased 50 percent, while power efficiency has improved 70 percent, compared to 2021's 2 nanometer process node. This efficiency leap matters for high scale cloud data centers and machine learning models.
In fact, researchers have projected an AI accelerator manufactured with 7 Angstrom technology could achieve 9,000 TOPS, a 6x leap over current hardware which averages 1,500 TOPS. Such a processing density could reduce frontier artificial intelligence models training cycle from 3 months to 2 weeks.
The major innovation was in using the z axis to stack the transistors in a 3 dimensional sequencial integration architecture which stagers and interrups the transistors compared to previous 2D chip architectures. This was achieved by designing an ultra thin dielectric wafer bonding process which enables multiple silicon sheets to be stacked with very low structural defects. This stacking architecture allows the channels of each transistor to be optimally designed seperately for the best performance, permitting different materials or materials combinations to be used in the n and p transistors for maximum energy efficiency. This was verified in hardware by operating a functional CMOS inverter.
In work presented at the VLSI Symposium, IBM has shown that Nanostack architectures can reduce the physical size of static random access memory by 40%. One of the major performance bottlenecks in supercomputing applications has been the on chip memory space. By shrinking this memory space in half, chip designers can fit over double the transistors onto a silicon slab the size of a human fingernail.
This represents a distance covered by almost twice the transistors as was possible on the 2 nanometer process of years past. Voluminous data bandwidth can now take place directly on the processor.
Fabrication to below 1 nanometer scale is extraordinarily demanding. It was at the IBM Albany NanoTech Complex, New York, that research toward this goal was carried out; the facility is about to receive the first installation of high numerical aperture extreme ultraviolet lithography toolset being developed by ASML. The company is currently working with tool builders, including Lam Research, TEL and SCREEN, to develop the chemistry and machinery capable of printing these circuits at atomic scale. The company also announced to develop Anderon as an independent spin off company that will be the first dedicated quantum processor manufacturing foundry, further expands the local foundries architectures.
