Samsung Semiconductor R&D Center Achieves Industry First 3D SFET Structure Overcoming Physical Limitations of Horizontal Scaling to Double Density
Samsung Semiconductor R&D Center has achieved the industry's first functional three dimensional stacked field effect transistor (3D SFET) structure, announced at the VLSI Symposium. This innovative structure overcomes the physical limits of horizontal scaling by stacking the transistors on top of one another. The Logic Technology Development Team, the creators of this technology, stated that the vertical structure represents the same architecture change that led to V NAND and High Bandwidth Memory.
As horizontal scaling causes transistors to be closer and closer together, the insulator layer that keeps neighboring transistors separate must also become smaller. Beyond its physical limits, electrical leakage and interference will prevent normal functioning of the chip. The vertical structure removes this restriction by having the insulator layer separating the top and bottom transistors formed vertically. This eliminates the need for a horizontally oriented insulator, meaning two transistors can fit in the same space as one did horizontally, therefore doubling the density of transistors.
The team's effort in reaching a gate pitch of 42 nm is the lowest achieved for any physically fabricated structure, compared to the prior industry record of 48 nm. Additionally, their vertical integration is more advanced than 2 2 nanosheets by implementing 3 upper and 3 lower nanosheets in a triple stacked configuration. A vertical interconnect formed by the RX Bounded Contact creates a direct electrical connection between the top and bottom transistors.
There were many chemical and etch challenges in the implementation of the vertical structure. Increasing the aspect ratio required finding new processes to excavate thin gaps in deep vertical trenches and deposit metal fills without any voids. In older transistor architectures, connections were made laterally by the C shaped wrap around contact, but this new RX Bounded Contact punches straight down. This new method requires a deep trench which is three times deeper than usual manufacturing, and therefore greatly increases complexity.
The strict submission deadline for the VLSI Symposium meant intense development for a long stretch. Team members from the process development side came in day after day for over 10 straight days, overlapping on weekends, over a national holiday. Engineers sacrificed personal plans to maintain laboratory operations, and when early wafer tests with the new masking materials yielded unexpected results, engineers reorganized, ran 4 iterations of experiments, and developed the process. Project managers said the team was able to overcome the difficult engineering challenges due to their experience with vertical scaling in flash memories, in addition to a one team spirit.
With two transistors now packed in the space where one previously fit, we were able to demonstrate a device with twice the transistor density.
The impact on artificial intelligence accelerators, HPC and server processors is expected to be significant. While the current scaling technique has yield performance gains of around 15% per generation, Doubling the transistors would offer a theoretical power efficiency of 2x, perfect for applications that requires more processing power in the same footprint with less heat output.
This achievement currently represents a working demonstration device rather than a finished, mass produced product. Having successfully demonstrated the n type and p type transistors stacking, the team states they have produced the fundamental building blocks of any future logic devices. Now, they aim to build the 3D SFET into a Ring Oscillator to confirm its functioning under active current and a high speed temporary memory block to verify storage reliability before pursuing full commercialization.
