Synopsys LPDDR6 IP Achieves Silicon Bring-Up on TSMC N2P Process for Next-Gen Mobile Memory

Synopsys announces the successful silicon bring-up of its LPDDR6 IP on TSMC's advanced N2P process.
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Synopsys LPDDR6 IP Achieves Silicon Bring-Up on TSMC N2P Process for Next-Gen Mobile Memory

Synopsys Achieves Silicon Bring-Up for LPDDR6 IP on TSMC's N2P Process

With the successful silicon bring-up of its LPDDR6 IP (Intellectual Property) block now based on TSMC's N2P manufacturing node, Synopsys has proclaimed a major entry into the domain of mobile memory technology. This milestone is an important step toward the commercialization of next-generation LPDDR6 memory for mobile devices.

Key Highlights of the LPDDR6 IP Development

Silicon bring-up means the first power-on and successful testing of a new chip or IP block. With the completion of this event, Synopsys finds itself in a position to offer a licensable building block of LPDDR6 technology for integration by other companies into their products. It is also among the first integrations of the TSMC N2P process into an LPDDR6 IP block.

  • Manufacturing Process: The TSMC N2P node, which is used for the PHY analog and I/O circuits.
  • IP Components: The basic components of the IP block are the controller (dealing with the JEDEC protocol engine and timing) and the PHY interface.
  • Performance Benefits of N2P: The TSMC N2P process attains remarkably impressive PPA (Power, Performance, and Area) figures. This corresponds to lesser energy consumption per bit, in turn offering lesser physical space for implementation opportunities, making it eminently suitable for on-device AI and power-efficient platforms.

Bandwidth & Performance Expectations

Synopsys's LPDDR6 IP stack was designed to meet high-speed needs of modern mobile applications. The company reported that bandwidth figures were achieved corresponding to JEDEC standards for LPDDR6.

  • Bandwidth Achieved: The IP block can show up to 86 GB/s of bandwidth.
  • JEDEC Per-Pin Rate: Corresponds to a per-pin data rate of around 10.667 Gb/s.
  • Theoretical Peak Speed: The LPDDR6 standard has a theoretical maximum speed of 14.4 Gb/s per pin, which translates to total bandwidth of 115 GB/s.

This is a significant upgrade over LPDDR5, with N2P tech from TSMC making critical contributions to realizing LPDDR6 memory standard next year in the mainstream.

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