New Capacitor-Free DRAM Achieved by Scientists in China
Chinese scientists are developing new DRAM-like memory cells that do not exploit a separate capacitor for function. The arrangement holds the density usual for DRAM and would be easier to manufacture and quite suitable for embedded and 3D memories.
How is the 2T0C Architecture Working?
The architecture has a new design of two-transistor and no-mechanism so-called 2T0C structures as opposed to the classical one-transistor, one-capacitor. The main change occurs in the mechanism of charge storage. While a conventional capacitor would hold a charge, this cell stores a floating charge in the transistor channel.
The charge of two bits of data can be stored in one cell by using four different levels of charge. Some of the key performance parameters include:
- Latency: Read-out timing has latencies similar to DDR5 (almost 50 ns).
- Data Retention: The cell maintains data for about 470 to 500 seconds, which is greatly longer than the retention time of conventional DRAM.
An Easier Process for Manufacturing
The reduction in cost arises from the simplified manufacturing process. Memory cells are made here using a self-aligned process on a prefabricated five-layer structure of IGZO (indium gallium zinc oxide) and tantalum with silicon dioxide layers in between. One lithography-and-etching step creates vertical depressions that become fully functioning transistors after further processing. A manufacturing process with fewer steps theoretically results in lower defect rates and lower production costs.
Present Status and Future Possibilities
These results are worth mentioning-done in a laboratory. The researchers did not divulge how the technology could be scaled commercially, where production conditions, such as the yield of usable chips, become important to the commercial viability.
The history of other memory technologies, such as ReRAM, MRAM, and FeRAM, shows that there can be a long delay between initial announcements and their availability in actual products.
