Intel's EMIB Technology and Chip Packaging
Computing applications like advanced artificial intelligence, machine learning, and high-performance computation (HPC) critically demand high data throughput with low latency. The Embedded Multi-die Interconnect Bridge (EMIB) technology is Chip packaging technology from Intel, which is expected to primarily meet these demands with high-bandwidth transfer of data between multiple dies (chips) integrated in a singular package.
EMIB in a nutshell
EMIB is the first 2.5D interconnect solution with small silicon bridges embedded directly into the package substrate in the industry. The traditional ways employ a large silicon interposer instead. By localizing the high-density interconnect only where it is needed, the EMIB offers a more flexible, power-efficient, and less expensive means of connecting heterogeneous dies.
EMIB has been in high-volume production since 2017 for server, network, and HPC products and is proprietary processes with proven technology.
Benefits and Features of EMIB
The EMIB architecture presents some unique advantages in dealing with complex semiconductor design:
- Heterogeneous Integration: It permits integration of large-complex die layouts from different process nodes into a single package.
- High-Speed Signaling: EMIB supports high data rates between adjacent dies with uncomplicated driver and receiver circuitry.
- Optimized Links: Individual die-to-die connectivity can be optimized by customizing the bridge for that link.
- Cost Efficiency: The tight microscale bump pitch is only required on the bridge, whereas the rest of the die can use a looser, more cost-effective pitch. This contrasts with full silicon interposers, which require a tight pitch all across the die.
- Power Delivery: The EMIB platform is enhanced with EMIB-M, incorporating Metal-Insulator-Metal (MIM) capacitors for better power delivery, while EMIB-T enriches standard EMIB with the inclusion of through-silicon vias (TSV) for high-bandwidth memory (HBM) applications.
Combining EMIB with Foveros Makes EMIB 3.5D
Intel brings an additional level of design flexibility by combining EMIB with its Foveros die-stacking technology. This hybridized method, known as EMIB 3.5D, integrates the vertically stacked chiplets of Foveros with the lateral, high-speed connections of EMIB.
This 3.5D architecture provides an optimized balance of package size, performance, power, and cost. It effectively overcomes constraints posed by thermal warpage and reticle size, facilitating the making of highly complex chip systems through greatly expanded silicon areas.
Leading the Shift from "System-on-Chip" to "System of Chips"
EMIB sits firmly at the heart of Intel Foundry's strategy to lead the industry from a SoC paradigm towards a chip systems framework. Disaggregated, chiplet-based solutions are enabled, and with industry standard support like UCIe, Intel offers advanced packaging technologies for the development of next-generation high-density, high-performance AI accelerators and other highly challenging silicon products.
