AMD 2nm Venice CPUs and Meta Partnership drive 2026 growth and financial goals for future earnings per share

AMD CEO Lisa Su outlines 2026 growth with 2 nanometer Venice CPUs a Meta AI partnership and MI450 series targeting a 1 trillion AI market by the year
AMD 2nm Venice CPUs and Meta Partnership drive 2026 growth and financial goals for future earnings per share

AMD Outlines 2026 Growth 2nm Venice CPUs and Meta AI Partnership

At the March 2026 Morgan Stanley Technology, Media & Telecom Conference, AMD CEO Lisa Su detailed the company's trajectory for the latter half of the decade. The company will achieve its financial goals through a 35% compound annual growth rate (CAGR) which leads to a target of $20 earnings per share (EPS) in future years. The company will achieve its goals through extensive AI infrastructure development and the adoption of new silicon technology.

The 6 Gigawatt Strategic Partnership with Meta

The most important operational change at the company includes a 6 gigawatt arrangement with Meta, which will change operations. The deal requires the creation of custom GPUs which will be designed exclusively for Metas AI requirements rather than normal hardware product sales. The agreement uses a performance based warrant structure to establish technological connections between both companies which will remain through multiple product development cycles.

The partnership will enhance AI training efficiency and large scale inference performance through its loading optimization activities. The agreement will enable AMD to enhance its software libraries and rack scale integration process through rapid development activities. AMD is tracking OpenAI deployment at the same level of scale which will begin with the first gigawatt of capacity deployment. The hardware products MI450 and Venice CPUs represent the next generation of computing technology.

The product cycle for AMD in 2026 will use the MI450 series accelerators and the upcoming Venice CPU line. The AMD chiplet architecture delivers high bandwidth memory benefits to AI workloads which require inference processing.

  • Venice CPUs These processors are on track to ramp in the second half of 2026. The Venice system uses TSMCs 2 nanometer (2nm) chiplet architecture to create a system which will take on greater market share in traditional computing systems.
  • MI450 Series The MI450 series functions as a comprehensive AI solution which includes both MI450 and Helios Rack systems. AMD is developing complete rack scale systems which use its Helios infrastructure built from the ZT Systems acquisition of main systems.

Su explained that CPU demand now exceeds previous estimates because of the need for balanced heterogeneous computing systems which must include both AI accelerators and CPU components. The system enables faster multi gigawatt cluster deployment in hyperscale data centers.

AMD faces multiple industry limitations while its future business prospects remain optimistic. The microprocessor market continues to experience supply shortages because current demand exceeds predictions which were made for 2025. Su announced that AMD possesses sufficient CoWoS capacity to meet the upcoming Q4 2026 volume increase.

The GPU product line will receive HBM4 memory through current integration planning activities. The MI325 series requires AMD to obtain licenses for distribution in China. The company continues to pursue Department of Commerce licensing for specific AI exports while operating in the competitive Chinese market. The networking roadmap will implement open standard guidelines which enable hyperscale data centers to choose between UALink and UALink over Ethernet as their preferred networking system.

AMD estimates that the AI accelerator market will reach a total value of $1 trillion by the year 2030. The company aims to achieve $120 billion in AI specific revenue to reach this target. The AI segment in data centers currently expands at an 80% compound annual growth rate which results from strong partnerships and a transition to agentic AI workloads that suit AMDs memory centric architecture.

AMD will continue to compete against traditional competitors and custom internal ASICs developed by cloud providers through its time to workload metric and its implementation of open ecosystem standards.

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