JEDEC Increases HBM Height Standard to Support 16 Layer AI DRAM Stacks and Advanced Semiconductor Bonding Technology
The Joint Electronic Devices Engineering Council has started official talks to expand the worldwide height requirements for High Bandwidth Memory. The industry requires this new height standard to support the development of 16 and 20 layer DRAM stacks which are necessary for modern artificial intelligence functionalities. The industry plans to increase the height limit to 900 micrometers which represents a significant jump from the 775 micrometer height limit that applied during initial HBM4 mass production. JEDEC intends to remove these physical restrictions because they hinder the production of thinner silicon chips which result in both lower production output and greater difficulties in thermal management.
The vertical height standard change produces new requirements for semiconductor assembly equipment. Memory manufacturers will continue using their current thermal compression bonders for high density stacking if the 900 micrometer limit receives approval. The development gives Hanmi Semiconductor a major market advantage because the company currently holds 71.2 percent of the worldwide market for these tools. Companies like Hanwha Semitech which focus on second generation hybrid bonding equipment development will need to wait more time before they can start commercialization. Hybrid bonding enables direct chip attachment without bumps but it requires manufacturers to spend more money and time compared to using traditional thermal compression methods.
Top memory manufacturers are investigating how the new standards will influence their current financial results and their future technological developments. SK Hynix representatives at the Semicon Korea 2026 conference stated that hybrid bonding will become necessary for stacks with more than 20 layers while height limit relaxation will benefit production efficiency in the present time. Samsung Electronics has developed hybrid bonding technology which provides better thermal resistance than existing manufacturing methods but the company can enhance its profit margins by using its existing production methods. The final equipment selection process will depend on the specific performance needs of important clients like Nvidia who require the new HBM modules for their GPU package designs.
JEDEC discussions are being monitored by the semiconductor industry because their results will determine which equipment providers will succeed until the end of the decade. The manufacturers main focus stays on reducing yield losses while they attempt to achieve maximum DRAM density levels. The market will experience a temporary period of stabilization between 900 micrometers and the development of hybrid bonding methods which will stabilize the market through advanced assembly solutions. Standardizing bodies and equipment accuracy and the needs of global AI infrastructure will determine the timeline for full scale introduction of next generation bonding according to technical experts.
