JEDEC Agrees on SPHBM4 Memory Standard Specification to Lower Artificial Intelligence Hardware Costs Through Standard Packaging and Enhanced Thermal Architecture
The Joint Electron Device Engineering Council (JEDEC) has come into agreement on a new memory standard to help lower the expense for hardware dedicated to artificial intelligence. As reported by etnews, the formal body of JEDEC decided on the specification for SPHBM4 after thoroughly deliberating the details within the DRAM subcommittee. Nevertheless, the new method is designed to keep the excellent records of next generation memory with the application of standard packaging instead of turning to costly and clever standards.
The SPHBM4 standard alters the basic physical configuration of high bandwidth memory. It is designed for a 4 fold jump in signal bandwidth over predecessing architectures, which therefore lowers the number of signal pins needed to just 1/5th of the normal count. This significantly scale down pin density enables system developers to use traditional substrate packaging and still receive the needed high scale bandwidth speeds of the AI computation.
Alongside pin optimization SPHBM4 also modifies the physical path for connections within the package. The new requirement allows for the host compute silicon and the memory stack to be separated by a physical distance of up to 20mm. This physical spacing affords chip architects a great deal more freedom when it comes to designing the thermal architecture for the overall system allowing heat to dissipate more effectively away from the main core during heavy processing loads.
This change to a structural means has piqued considerable industry interest in glass substrates as an alternative to organics. Glass provides better thermal stability, flatness and ability to route fine circuitry. Due to the high fabrication cost of glass technology, it has yet to be adapted for mass production, though the SPHBM4 technology could help speed the process along. Industry experts are quick to note that although the glass substrates are the basis of large scale semiconductor package construction, this SPHBM4 technology allows for the layouts of the memory within that package to be far more cost effective.
To be fully adopted, however, the proliferation of SPHBM4 will have to rely significantly on ecosystem collaboration. This multi directional adoption can only happen when memory vendors like Samsung Electronics and SK Hynix start building the hardware. Foundry leaders such as TSMC, and chip designers including Nvidia need to chip their SPHBM4 designs into their future AI systems.
