New Monolithic Three Dimensional Silicon Chip Integration Technique Using Low Temperature Bonding and Vertical Stacking to Overcome Thermal Limits
While physical scaling limits are threatening to bring an end to the relentless advance of Moores Law, University of Illinois Grainger College of Engineering researchers have devised a new fabrication technique that circumvents these limitations. The method, described in the journal Nature, presents a scalable technique for building up high performance silicon circuits one atop the other vertically. Researchers, led by materials science and engineering associate professor Qing Cao, have determined a method of building up rather than packing more and more transistors onto a flat silicon surface.
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| Schematic (left) and false-colored electron microscopy image (right) of a monolithic 3D static random-access memory cell, featuring six transistors distributed across three vertically stacked layers. |
The current silicon chip process involves a thermal budget reaching 1000 C, needed to create high quality semiconductor devices. Once the first layer of circuits are formed, no more can be fabricated above it if the processing temperature reaches above 400 C, as this would destroy the underlying metal wiring. This has limited monolithic three dimensional integration an alternative approach to shrinking chip dimensions by creating each successive layer of circuitry directly on top of the one beneath it as silicon only withstands a narrow thermal window. Researchers have turned to other materials such as carbon nanotubes or metal oxides, but these technologies have suffered from both low electrical performance and lack of reliability when implemented into new circuitry layers.
To overcome this thermal limit the Illinois team developed a transfer technique employing a specialized roll laminator. Ultrathin freestanding single crystalline silicon nanomembranes of less than 10nm thick were fabricated on a donor wafer, then transferred onto a receiving wafer with the bond temperature held at just 200 C. This low temperature bond has a profound effect in allowing the underlying metal connections to remain intact while preserving the crystalline structure of the new silicon layer.
To circumvent the 600 C temperatures required to make locally doped, junctionless transistors were used. Due to the ultrathin dimensions of the transferred nanomembranes, the gate maintains full electrical control over the heavily doped channel which enables the dramatically decreased parasitic contact resistance. Distributing devices vertically helps both shrink silicon circuits spatial footprint and simultaneously increase the rate of data transfer across layers.
As explanation for the structural efficiency of vertical placement materials science and engineering associate professor Qing Cao described,
Six microelectronic devices called transistors on a single plane are currently needed to hold one bit of data. Using vertical integration one can spread these across several layers of circuitry. It s like stacking several suburban apartment complexes into a single multistory building same function, just smaller space, while increasing transfer speed between layers.
The experimental yields of the devices constructed are very encouraging for industrial scalability. From within the academic cleanroom the team was able to achieve yields between 98% and 100% while integrating 3 layers of circuitry, each containing 625 transistors and output current densities 3 to 4 times higher than existing 3D circuits fabricated from alternative materials. The uniformity is highly indicative of industrial feasibility.
This research was conducted in the Center for Advanced Semiconductor Chips with Accelerated Performance which involves numerous industrial partners such as Intel, IBM and TSMC (Taiwan Semiconductor Manufacturing Company). This program aims to transfer the monolithic 3D process from academic laboratories into industrial fabrication facilities. Other authors who contributed to this work include Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu Chih Ni, Shomik Chatterjee, Shaloo Rakheja, and Jian Min Zhuo.
