TSMC Glass Substrate Packaging Transitions From Circular to Square Form Factors for Advanced AI Supply Chain Readiness
There is a huge demand in large area, complex heterogeneous integration through advanced packaging due to the proliferation of AI processors which are heavily utilizing High Bandwidth Memory. In a response to Chip on Wafer on Substrate’s physical size constraint, the TSMC is now speeding up the pace on Chip on Panel on Substrate, which utilize glass substrate instead of conventional organic substrate. The major challenge is the rate in which the glass core substrate’s yield can be improve.
In a recent analysis released by udn, Liu Pei chen, data director at the Taiwan Economic Research Institute database, pointed out the nature of competition is shifting. The evolution of panel level packaging is expanding advanced packaging from beyond the scope of “wafer level,” transforming it into “panel level,” and the key in the fight is panel sizes and new materials. TSMC is striving to establish an early lead for the advanced packaging eco system, as future GPU may need a packaging solution of a much larger footprint.
The previous manufacturing process uses 12 inch silicon wafer (circular wafer), but this leads to a wasted area due to geometric incompatibility. When you need to package a large, square chip using the conventional packaging technique, the material usage rate is generally under 70% . This is why the adoption of the new panel packaging technique that utilizes glass substrate is a critical decision, explained Liu Pei chen in the udn article. With the shift towards a square panel from the conventional circular panel, TSMC can now reach more than 90% material utilization rate, effectively bringing down the high cost caused by geometrical loss for those oversized semiconductors’ mask reticles.
According to market data by trend force, TSMC’s target for early stage substrate size is 310 x 310mm, and we’re now in the midst of verifying materials and tools, with pilot production in 2027 and mass production later in the second half of 2028. The total adoption of the glass core will not likely occur until after 2030. We hear there may be initial pilot lines for that on TSMC’s sister companies (like VisEra), and the production may extend to VisEra’s facilities at its Chiayi site or to an Arizona fab over the next couple of years.
The use of Through Glass Via (TGV) is also crucial. Organic material causes warp and is susceptible to uneven thermal expansion rate under huge thermal load. By using the glass core substrate for advanced packaging application, this improves the warpage index by 16% and reduces electrical inductance and resistance to significantly enable large packages size for more dies.
While those electrical and structural advantages make glass core a perfect fit for massive packages, glass isn’t perfect as a chip packaging material. Glass is an extremely brittle material that a microscopic scratch might evolve into structural damage under stress. Also, the electrical conductivity is not as good as silicon, creating challenges for high power applications. Besides, since glass based substrate has not been adopted before on massive chip package, it requires an ecosystem with many new equipment and processes before mass production becomes viable.
TSMC’s Taiwanese partners are already working hard to develop new equipment and machines that are specialized for the panel glass packaging. Manz Automation, a partner of TSMC that is producing automated equipment and systems for solar, electronic device, and semiconductor applications, is preparing tools for TGV metallization and RDL processing. InnoService is expected to have its copper column deposition machines ready for mass production by 2027. Meanwhile, Scientech, Grand Process Technology, are expected to provide wet processing and cleaning tools, and Chroma is developing panel inspection tools. Star technology, is developing the drilling tools and Gu Deng is offering carriers and transport solutions for panel substrate handling.
