Huawei Advances Kirin 2026 Development via LogicFolding Architecture and Post Moores Law Scaling Theory for High Efficiency Silicon
Huawei has set its engineering framework for the upcoming silicon generation by releasing the second version of its post Moores Law scaling theory. The academic paper on ChinaXiv, the scientific preprint website published by Huawei, notes that Tingbo He, the head of the Huawei Semiconductor Unit, is the author of the latest version. Under the title Time Scaling Theory for Multi Layer Electronic Systems, the research extends practical engineering steps to drive the production of the Kirin 2026 with a focus on temporal rather than physical scaling of transistor feature size.
The second version of this paper builds on the first which was released earlier this year. While the publishing of the first paper established the theoretical concept of casting the time constant defined by the Greek letter tau as the primary metric of progress, it did not include engineering measurements. This new research paper comprises eight chapters that direct a path to design digital, analog, and memory circuits through a vertical integrated semiconductor structure.
The key technology progress contained within the paper is an architecture called LogicFolding. While standard 3D semiconductor production involves stacking silicon at the macro block level, combining different functional blocks such as logic and memory, the new process from Huawei leverages an equivalent of a gear ratio. When the physical pitch of the hybrid bonding process is on par with the width of the top level metal wires, the design space permits cell level continuous optimization.
The process allows digital, analog, and memory transistor clusters to be placed across vertically enabled levels on a spatial grid. This approach is no longer subject to the blocky, separate layers of reduction found in prior process nodes. Within the empirical data published, the proposed LogicFolding architecture achieves a 55% stepwise increase in overall transistor density as well as a 41% improvement in total system power efficiency at a fixed node. The process enables a system to attain improved performance and cellular density without the requirement of next generation Extreme Ultraviolet lithography machinery.
The paper also contains performance tables comparing the anticipated Kirin 2026 silicon with the baseline Kirin 9030 Pro profile. The data tables specify the exact Voltage, Frequency, Normalized Power, Die Size, and Power Density of the next generation processor. The architecture utilizes a series of dependent technologies including a spatiotemporal model, a Unified Bus interconnect framework, and the Hi ONE optical engine to facilitate high capacity data transfer between multiple stacked layers.
The roadmap sets a path for mobile and AI hardware upscaling, including the steps in shifting through silicon vias from the top metal layer to the M6 layer and eventually onto multi active layer stacking for mobile chips. Additionally, the paper provides details on how these principles of temporal scaling will be bolstered through future iterations of the Ascend series AI accelerators. By focusing on time delay reduction instead of the physical reduction of gate length, the company seeks to establish a self contained semiconductor pipeline capable of functioning independent of Western manufacturing equipment.
