Intel Foundry is scaling up its domestic chip manufacturing to meet the massive processing demands of modern artificial intelligence. The company is shifting away from building single giant processors in favor of advanced packaging that links smaller specialized chiplets together. However, achieving this level of silicon integration requires massive investments in specialized factories.
The heart of this effort is centered at the Fab 9 facility in Rio Rancho New Mexico. What began in 1980 with just 25 employees has grown into a massive operation with 2700 workers and 500 local suppliers. Fab 9 manager Katie Prouty explained that the site originally led the industry in 6 inch wafer manufacturing back in the 1980s. Today, the facility has adapted to become the leader in the United States for assembling these complex silicon mosaics.
To package these tiles, Intel relies on a vertical stacking technology called Foveros. Principal Engineer Chris Seibert compares the process to building a pizza. The base layer is a silicon interposer, which acts like a pizza crust. A specialized tool places the individual chiplets on top of this base before sending the entire assembly to a machine that bakes the components together. An epoxy layer is then added to seal the parts, and water cooled blades slice the finished wafers into individual units.
This stacking method allows different chips from various designs to function as a single unit. It helps laptop batteries last longer by placing demanding circuits on more power efficient process nodes. Devices can become thinner and smaller without sacrificing overall performance.
For side by side connections, the company relies on an Embedded Multi Die Interconnect Bridge, widely known as EMIB. Instead of using expensive silicon layers across the whole package, EMIB places tiny silicon bridges only where the chiplets need to communicate. The latest 2026 advancement is EMIB T. This version routes power directly through the silicon bridge rather than around it. This design choice improves power efficiency and meets the massive bandwidth needs of modern memory chips.
This approach allows Intel to scale packages to 8 times the industry standard, with plans to reach 12 times by 2028. Customers are starting to approach the foundry specifically for these advanced packaging options. Prouty mentioned that successfully delivering on these projects is helping the company build long term trust with external clients. By mixing and matching silicon from different sources onto a single platform, the company can construct the massive processing units that run modern data centers.
