NVIDIA has unveiled the Vera CPU, a custom chip engineered to handle the irregular workloads of agentic AI. The processor ditches traditional design choices by focusing on high single thread speeds and memory access over massive core counts. But the true test will be how it scales across massive AI data centers.
Agentic AI behaves differently than standard code. Instead of waiting for a single prompt, AI agents run continuous cycles of code execution, database queries, and tool orchestration. NVIDIA calls this process the agent loop. Because these loops run concurrently across thousands of systems, CPU delays can stall the entire network. Olympus, the custom Arm microarchitecture inside the Vera chip, targets these exact bottlenecks.
The Olympus core uses a 10 way decode front end to keep instructions flowing smoothly. It relies on a neural branch predictor to anticipate complex software paths. This is vital for agent workflows, which often feature unpredictable branch logic and heavy memory lookups. A deep out of order execution window helps the core discover independent operations while earlier tasks wait on memory. The cache subsystem also includes a graph prefetcher to speed up pointer heavy data structures.
Multithreading is necessary when sandboxes run background tasks alongside the main execution path. Traditional simultaneous multithreading can cause performance conflicts when threads fight for execution resources. NVIDIA addresses this with Spatial Multithreading. This system partitions internal execution resources between 2 hardware threads, giving maximum power to 1 thread when needed or isolating them to prevent interference. Each Vera socket holds 88 cores and 176 threads to manage large workloads.
A fast core is useless if it starves for data. The Vera CPU connects the cores using the Scalable Coherency Fabric, which provides 3.4 TB per second of bandwidth and a 164 MB L3 cache on a single monolithic die. This design avoids the latency penalties of chiplet based platforms. For memory, NVIDIA uses SOCAMM2 LPDDR5X modules instead of DDR5. This subsystem delivers 1.2 TB per second of total bandwidth and reduces memory latency under heavy concurrent loads by 40 percent.
For larger scale deployments, Vera uses second generation NVLink C2C links to connect 2 sockets coherently. This creates a dual socket platform with 176 PCIe 6.4 lanes and CXL 3.1 support. Unlike chiplet processors that present a fragmented memory landscape, each Vera socket acts as 1 clean NUMA node. This software first approach makes code tuning simpler. Data remains secure across these links through hardware level VM isolation and authenticated C2C encryption.
Early laboratory data shared by NVIDIA indicates that the Olympus core achieves up to 2x higher single thread performance under load compared to current x86 processors. Sandbox start times and task completions ran roughly 2x faster in developer tests. For data streaming, joint tests with Redpanda and HPE showed up to 6x higher performance, while scientific tasks ran up to 7x faster than an Intel Sapphire Rapids setup. These gains show that reducing CPU wait times is becoming the next battleground for hardware efficiency.
