SK hynix took center stage at the TSMC OIP Conference to reveal its next generation memory hardware powering NVIDIA upcoming superchips. The Korean chipmaker showed off its latest 12 layer HBM4 silicon alongside SOCAMM2 modules running inside the Vera Rubin platform while taking home a top partner award for the 2nd straight year. But the real surprise came from its future storage roadmap, which plots a massive shift toward modular chiplet controllers.
Visitors at the Santa Clara event saw the hardware up close inside NVIDIA flagship AI platform. The live setup connected the Vera CPU and Rubin GPU with 12 layer 36GB HBM4 stacks to eliminate latency bottlenecks during complex matrix calculations. Main system memory ran through a 96GB SOCAMM2 module, built specifically to feed high volume data to the CPU so software agents can track conversational context instantly. That setup was not alone. SK hynix also displayed early 16 layer 48GB HBM4 units and a massive 192GB SOCAMM2 board ready for larger server racks.
The product display coincided with TSMC granting SK hynix its Partner of the Year Award in advanced 3DFabric integration. The win marks back to back recognition for the memory maker, this time for running validation trials of future HBM5 stacks on TSMC CoWoS packaging. Stacking memory higher demands tight collaboration between foundries and memory suppliers from the drawing board. Isolated silicon design is practically dead.
Data center racks are burning through power, and SK hynix aimed several new products directly at the thermal problem. The company presented a 256GB 3DS RDIMM alongside the world first 64GB RDIMM produced on a 10 nanometer class sixth generation process. High bandwidth 128GB MRDIMM hardware also appeared on the floor to target memory heavy server tasks.
Storage received an equal push. The PEB210 enterprise SSD arrived with built in compatibility for direct liquid cooling, drawing steady attention from operators running dense server clusters. The team also rolled out the PS1101, marking the manufacturer first enterprise drive using QLC flash to maximize total storage space per server slot.
During a joint technical session with Cadence, PCIe design engineer Daesik Park laid out the rapid growth facing enterprise data pipelines. Park projected the enterprise storage footprint will expand roughly 3.8 times, jumping from 509EB to 1,933EB by 2030. Meeting that demand requires rethinking the controller silicon entirely.
Since the fourth generation, a new generation has arrived every 2 to 3 years, doubling bandwidth each time, and from the sixth generation in particular, power optimization and collaboration between design and process have become even more important.
To keep up with upcoming sixth and seventh generation speeds, SK hynix is breaking away from traditional single die controllers. The firm is currently developing modular controller chiplets connected through open UCIe links. Park explained that this layout cuts engineering schedules, allows teams to upgrade specific controller blocks independently, and keeps thermal limits under control as server storage speeds double again.
