Micron outlined its next generation memory and storage roadmap, detailing vertical vHBM architectures, G11 flash reaching beyond 400 layers, and sub 10 nanometer DRAM nodes. The technical presentation confirms the company will bypass 4F square cell layouts entirely to prioritize true 3D DRAM development. Production schedules across these advanced nodes begin rolling out through 2027 and 2028.
Engineers project vertical vHBM and edge focused vEIM memory will arrive alongside standard HBM5 in 2028. Vertical vHBM stacks DRAM dies, a base die, and an XPU logic processor directly on top of each other. This direct vertical stack shortens data communication pathways, increasing overall bandwidth efficiency while cutting power consumption. For edge AI inference, vEIM targets 2TB per second bandwidth with energy efficiency under 1 picojoule per bit. Both memory designs rely on bumpless hybrid bonding coupled with integrated thermal solutions, running alongside standard 2.5D packages.
Flash development shifts toward G11 architecture scheduled to ramp volume production in the second half of 2027, skipping the G10 generation entirely. G11 stacks more than 400 layers using wafer to wafer bonding techniques. This design delivers 2 times the areal storage density of previous 276 layer G9 chips, alongside 1.5 times the input output speed and a 25% drop in transfer power consumption. Future architectures plan to introduce high mobility channel materials for even denser cell structures. Datacenter hardware will also gain 2 dedicated designs, including single level cell storage optimized for GPU direct access and bandwidth focused configurations.
Scaling limitations on 4F square cell layouts prompted the firm to abandon the architecture after 2 decades of testing, shifting all future capital toward 3D DRAM. The current seventh generation 10 nanometer node, designated 1 delta, is already in yield production and delivers a 25% density improvement. The upcoming 1 epsilon node introduces wafer bonding. Looking further ahead, the first sub 10 nanometer node, designated zeta angstrom, enters early development utilizing High NA EUV lithography tools, followed by eta angstrom which relies on experimental materials. Micron is also transitioning DRAM CMOS logic circuits into 3D arrangements to boost operational speed.
