More info has come out about AMD's soon-to-come SP7 and SP8 server setups. They will run the new EPYC chips named "Venice" and "Verano." These setups aim to boost memory speed and links with fast DDR5 RAM and the new PCIe 6.0 tech.
After AMD's news on EPYC Venice (Zen 6C, up to 256 cores, coming in 2026) and EPYC Verano (maybe Zen 7, in 2027), some in the know have shared more about the tech behind these chips.
The SP7 is made for tough jobs in big firms and data centers. It plans to have:
- Memory Could use up to 16 ways of DDR5 memory. This includes ECC memory at speeds up to 8000 MT/s and MRDIMMs going to 12,800 MT/s in a one-DIMM-each-way setup. It will also support kinds like RDIMM, 3DS RDIMM, and Tall DIMMs.
- Links (I/O) Units with two sockets (2P) could have up to 128 PCIe Gen 6.0 ways, each with 64 Gbps of speed. They might also have up to 16 more PCIe Gen 4 ways. Units with one socket (1P) could get up to 96 PCIe Gen 6.0 ways and 8 extra PCIe Gen 4 ways. Also, the setup is set to have Smart Data Cache Injection (SDCI).
Made as a start-level choice but still ready for new EPYC chips, the SP8 will share memory use with SP7 but with 8-channel setup. SP8 could also have more PCIe Gen 6.0 links:
- Memory Up to 8 ways of DDR5, with speeds up to 8000 MT/s ECC, 12,800 MT/s RDIMM, and support for different DIMM types like SP7.
- Links (I/O) Units with two sockets (2P) might get up to 192 PCIe Gen 6.0 ways, plus 16 PCIe Gen 4 ways. Units with one socket (1P) could have up to 128 PCIe Gen 6.0 ways and 8 PCIe Gen 4 ways.
The new Zen 6C "tight" cores, likely in the Venice line, could have up to 32 cores each. With eight of these, it's set to reach 256 cores as AMD said. Each one could also have 128 MB of L3 storage, making 1 GB total.
These chips should have two IO parts, each with PCIe Gen 6.0 / CXL 3.1 tech, support for DDR5-8000 memory (some plans hint at MRDIMM speeds up to 10,400 MT/s), Gen4 Infinity Fabric, and a Secure Processor.
Regular EPYC "Venice" CPUs using normal Zen 6 cores might have 12 cores each. With eight of these, it could mean 96 cores and 192 threads, like AMD's high-end Turin now.
On power, EPYC SP7 chips might need about 600W, while SP8 chips could need between 350-400W.
These steps show AMD's focus on raising core counts, computing power, and I/O in its server gear. As EPYC Venice and Verano CPUs start in 2026 and 2027, the data center area looks set for big new things.
AMD also stressed the key part of strong server CPUs today, especially with AI growing. The right mix of CPU and GPU can change how well AI jobs go. Though exact figures must be checked, the key point is that strong CPU setups are a must for growing needs of data centers, notably those with AI tasks.
