Rapidus 2nm Chip Making Faces Tough TSMC Fight Says Pat Gelsinger as Japan Pushes for 2027 Production

Japan's Rapidus prepares for 2nm chip making by 2027, facing a tough fight with TSMC. Pat Gelsinger warns about the challenges for the new venture.
Rapidus 2nm Chip Making Faces Tough TSMC Fight Says Pat Gelsinger as Japan Pushes for 2027 Production

Rapidus Gets Ready for 2nm Chip Making, But It's a Tough Fight with TSMC

Japan's Rapidus is pushing ahead to take on big chip makers with its 2nm tech, aiming to start making lots of chips in 2027. They plan to bring high-tech packing into the same place to make things faster. But, Pat Gelsinger, who once led Intel, thinks this might not be enough.

Rapidus's 2nm Chip Plant in Japan

A Warning from a Long-Time Expert

At a news talk in Tokyo, Pat Gelsinger shared tough words about Rapidus's chances. According to the Japan Times, he said:

"We cheer for Japan's work to launch Rapidus. Yet, Rapidus needs new standout tech, for if they just try to catch up to TSMC, who is doing great, it will be a very hard road."

What Rapidus Wants to Offer: All-in-One Making

Rapidus wants to make everything faster at one spot with a new system to pack chips, trying to speed past rivals like Samsung, Intel, and TSMC. But, this won’t be ready from the start; they'll first only work on making test chips without the packing services.

Plans and Dates

Rapidus plans to start test runs on its 2nm tech, using GAA transistors. They've set a few big goals:

  • Wafer Samples: They plan to have the first samples out by July.
  • Design Tools: Early clients will get tools to start making prototypes.
  • Big-Time Making: They want to start big-scale making with the 2nm tech by 2027.

Building and Research Moves

Big steps are happening at Rapidus's site in Chitose, Hokkaido. They put in advanced chip-making machines last year, prepping for test runs.

Also, Rapidus is starting a new research spot named Rapidus Chiplet Solutions next to Seiko Epson. They'll work on:

  • Building up extra layers.
  • 3D packing tech.
  • Creating design tools.
  • Ways to test good chips, like HBM parts.

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