Huawei Kirin 9030 Chip Takes Full Advantage of SMIC's N+3 Chip Technology
Microelectronics research company TechInsights confirmed that Huawei's new HiSilicon Kirin 9030 is manufactured using SMIC's latest and most advanced N+3 fabrication process. Although the technology allows for performance gains of Huawei's Mate 80 series smartphones, the analysis set forth earlier indicates it is really just an incremental extension of existing 7nm-class technology, and not at all on par with the 5nm processes offered by industry leaders such as TSMC and Samsung.
What is N+3 Technology
Both Kirin 9030 and 9030 Pro chips have increased core counts (12 and 14 cores, respectively) when compared with the earlier eight-core Kirin 9000 chips from 2020. In conjunction, the Mate 80 Pro Max is reported to show an overall performance improvement of 42%, and these hints pointed to a new manufacturing node.
TechInsights performed structural analysis, which confirms the use of the N+3 by SMIC. However, it is best described as a very advanced evolution of SMIC's own existing 7nm (N+2) technology. It is not really a generation jump to 5nm but rather a node that is in-between without being able to access the advanced Extreme Ultraviolet (EUV) lithography tools.
The DUV Lithography Challenge
SMIC is dependent on pushing DUV lithography tools to their extremities, standing by their progress. SMIC is known for producing multi-patterning techniques in complexity to make the smallest features possible, which involves doing multiple etchings, line up those lights extremely.
Rajesh Krishnamurthy at TechInsights indicated that this would happen with "significant yield challenges". The main risk areas appear to relate to the back-end-of-line (BEOL) interconnects where aggressive use of DUV multi-patterning gives rise to defects and can cause production yields to plummet if misalignment is anything less than perfect.
Incremental Improvement Rather than Breakthrough
Analysis indicates that there has not been any significant difference in the fundamental transistor geometry FEOL between the previous N+2 node and now. However, gains from N+3 are extracted through design technology co-optimization and complex BEOL.
It is in this assertion that SMIC can improve area density in chips without using EUV but at an increasing quickly cost with a continuously narrowing margin of errors. The significant innovation of the N+3 process in constraints points out the continued technological gap with other foundries that access EUV technology.
Implications for Future Developments
The Kirin 9030 demonstrates China's internal advancement in the development of domestic semiconductor technologies in spite of outside restrictions. However, future shrinks will be dependent exclusively on DUV multi-patterning; this is a path into which severe limits will be very clearly outlined. In fact, future development in SMIC will depend on more design discipline and advanced packaging solutions than on lithography reductions, especially in the case of mobile SoCs where advanced packaging applies less.
