Huawei Announces New Semiconductor Path With Tau Scaling Law Strategy To Drive Transistor Density And Performance Through Time Scaling Innovation
During a keynote address at the IEEE International Symposium on Circuits and Systems, a representative from Huawei, He Tingbo, announced a paradigm shift in the theory of semiconductors, the New Semiconductor Path in Practice. In her speech, He Tingbo presented the Tau scaling law, a design methodology designed to lead the evolution of integrated circuits. The strategy aims to replace the traditional geometric scaling with a system based on time scaling, using the speed of signal propagation as a means to drive the density of the transistors on silicon and overall performance of the hardware.
For more than half of a century the semiconductor industry has been dominated by Moore Law, which states that the density of transistors doubles over a given time frame, resulting from physical shrinking. However, physical boundaries, along with the tremendous increase in fabrication costs, have hampered geometric scaling. The Tau scaling law looks to overcome this limitation by focusing on the decrease of the constant time in an electrical circuit, a measure that could allow development to continue on a path where demand is continually increasing.
Device level At the base level, engineers are hoping to decrease the resistance and parasitic capacitance of a single transistor, as well as that of the microscopic wires linking together each transistor and the rest of the circuit. This direct approach will decrease the time constant of the hardware.
Circuit level Huawei hopes to achieve the reduction of the time constant at the circuit level with the implementation of a new design structure, named LogicFolding. The process works by restructuring traditional circuits in a manner that decreases the distance across which the signal must travel, thus reducing the load on each electrical signal and increasing the density of the transistors on silicon.
Chip level The development teams will work towards optimizing all aspects of the hardware, including the instruction set, data flow, hardware architecture and silicon process. By streamlining the execution of workloads based on tailored data and instruction streams, the system's architecture can be improved to decrease overall processing time.
System level UnifiedBus, a new system protocol, is designed to revolutionize communication between elements of a computer system. Through unified memory addressing and native memory semantics of a high density cluster system, the time it takes for data to travel between processing units will decrease.
Huawei is not new to the use of the Tau scaling law. In the past 6 years, they have already implemented 381 chips designed with it. This coming August, it is projected that the newest generation of Kirin processors will be the first to commercialize a LogicFolding chip, yielding practical results. The long term goals for the architecture indicate impressive manufacturing equivalence. By 2031, the company expects the most efficient Kirin processors based on the Tau scaling law will possess a transistor density equivalent to a 14nm process.
To solve these worldwide problems in semiconductor design, He Tingbo encouraged a collective effort, "We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry. No single company can independently find all the answers along the path of semiconductor evolution. With the Tau scaling law, we look forward to working closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries."
