PSMC 3D WoW Wafer on Wafer Stacking Overcomes the Memory Wall Bottleneck to Support Massive AI Memory Density and Bandwidth
With current and expected trends for generative AI and HPC use, power and memory bandwidth has become two significant hurdles for current hardware architectures. To counter this, PSMC (Powerchip Semiconductor Manufacturing Corporation, 6770) is taking advantage of their logic and memory foundry experience and deploying a new path for silicon designers, using their advanced 3D WoW Wafer on Wafer chip bonding stack.
For their Computex presentation, PSMC created the 3D AI Foundry display as part of their efforts to display and deliver 3D WoW DRAM stacking along with required ancillary advanced packaging technologies including Silicon Capacitors (or IPD Si Cap) and Interposer silicon. According to PSMC they have been working together with the client's IP and product designs in order to support market needs for the massive memory density, memory bandwidth, and reliable electrical properties.
Current advancements and growth in artificial intelligence models have further amplified the historical hardware problem called the Memory Wall, which states that memory access speed has failed to catch up with logic processor speed. With the 3D AI DRAM being bonded directly with the logic processor chips this has effectively removed this bottleneck as data now has much less physical distance to cover to perform operations. This has the dual advantage of both increasing performance while also shrinking the thermal budget for the overall design.
Instead of operating alone, they have been working on an open ecosystem to speed up this technology and adoption. PSMC presented functional 3D WoW wafer stacking design and integrated product architecture, enabled by a collection of well known semiconductor partners including AP Memory, ESMT, Zentel Japan, Chip Integration Technology, and Powerchip Microelectronics (in logic) who provided IP designs for the exhibition.
