Cadence has certified its AI driven design tools and reference flows for Intel leading edge chip manufacturing nodes. The software now supports the latest Intel 18A P and Intel 14A process design kits to help engineers build complex mobile and artificial intelligence processors. But chip designers will still need early access agreements with Intel Foundry to deploy these workflows immediately.
This certification gives engineering teams a signoff ready path to manufacture chips on advanced production nodes. The partnership focuses on optimizing silicon design, packaging support, and power delivery architectures for next generation mobile and aerospace chips. The goal is faster production. According to the joint announcement at the Design Automation Conference, the integration builds on a multi year agreement between the 2 companies to align their design technology.
The updated software suite is tailored to exploit Intel latest manufacturing advances. This includes RibbonFET Gate all around transistors and backside power delivery systems known as PowerVia and PowerDirect. By matching these physical process upgrades with Cadence design tools, engineers can improve chip power and speed while shrinking the physical area. Intel senior vice president Shawn Han explained that co optimized flows give customers greater confidence to turn ambitious ideas into reality on next generation technologies.
Designing modern chips also requires advanced packaging to connect multiple silicon dies. To solve this, the 2 companies jointly developed a workflow that supports Intel Embedded Multi die Interconnect Bridge packaging. This setup simplifies the design of complex chip architectures by eliminating data conversion steps. It allows engineers to analyze thermal and signal issues early in the design process. Cadence representative Boyd Phelps stated that the collaboration gives design teams a trusted path to meet their performance and time to market goals.
Practical testing has already begun. The partners have successfully validated physical test chips on the Intel 18A process using Cadence memory and interface hardware. This step proves that the software and silicon work together in real world scenarios before mass production begins. Cadence is showcasing the newly certified workflows and packaging designs at its conference booth this week.
