Nvidia has deployed its new Vera processor to accelerate electronic design automation workflows for its own silicon development. The custom CPU features 88 Olympus cores and generation 2 Scalable Coherent Fabric to speed up complex chip simulation. But the hardware is currently restricted to internal testing and development with partners like Cadence and Synopsys.
Creating modern processors requires extensive logic simulation and verification before any physical silicon is manufactured. While graphics processors and artificial intelligence speed up many parts of the pipeline, essential design steps still depend on fast central processing unit cores. Chip designers must run thousands of mathematical iterations to catch errors, making raw per core performance a major bottleneck in development timelines.
To address this bottleneck, Nvidia collaborated with industry leaders Cadence and Synopsys to optimize software for the new architecture. Early testing on the Cadence Jasper formal verification platform and the Synopsys VCS simulation tool shows a performance increase of up to 1.5x compared to existing setups. Both software suites managed to process heavy workloads much faster while using the same number of cores.
The Vera system achieves these speeds by combining 88 custom Olympus CPU cores with high bandwidth LPDDR5X memory. A generation 2 Scalable Coherent Fabric connects these elements, ensuring low latency during massive regression tests. This combination allows engineers to complete more validation runs in a shorter period, shrinking the time required to go from register transfer level descriptions to physical silicon.
Using its own processors to build the next generation of chips creates a continuous development loop. Nvidia plans to expand this methodology by optimizing more software applications ahead of future releases. The company is already working on a successor called the Rosa CPU, which will use the newer Rigel core architecture to keep pace with growing design demands.
