GPU startup Bolt Graphics has completed bring up testing for its Zeus architecture test silicon, designed to combine dedicated electromagnetic simulation hardware with path tracing acceleration. The company verified the initial silicon on TSMC 12nm node at 1.4W without functional errors. Commercial chips built on TSMC N5P process are scheduled for a full market rollout in 2028.
Bolt designed the Zeus architecture for heavy computational workloads that combine simulation physics with graphics rendering. Dedicated hardware blocks handle electromagnetic simulation alongside accelerated path tracing calculations. This dual capability targets physical AI environments where real time simulation data interacts directly with visual compute pipelines.
The initial tape out verified the core design using TSMC 12nm process. This small test die measures 6 square millimeters, consumes 1.4W of power, and returned from fabrication in A0 stepping with zero functional defects. Commercial products will move to the advanced TSMC N5P node instead. Bolt plans to open developer access in 2027 Q1, ship initial hardware to early access partners by late 2027, and begin mass production of PCIe cards and server units in 2028.
