Data bottlenecks are slowing down modern artificial intelligence workloads. SK hynix presented its next generation memory solutions at the OCP Global Summit in San Jose to tackle this infrastructure limit. Live hardware demonstrations confirmed that memory pooling across servers doubles throughput while cutting operational power demands.
Live demonstrations highlighted the generation 2 CMM DDR5 module built on the CXL 3.2 interface. This 256GB unit reaches 80GB per second in bandwidth and improves electrical efficiency by 30% over earlier hardware revisions. By pooling memory across separate server nodes, the system removes bottlenecks during data heavy processing. Joint tests conducted with NAVER Cloud verified that pooled cache memory accelerates multi modal workloads and autonomous AI agent operations.
Engineers also showcased the MARS architecture, an AI rack system that clusters memory pools alongside processors from partners like AMD and Marvell. In live tests, this configuration stored and reused large language model caches through pooled DRAM and solid state drives instead of slow network links. SK hynix paired this with the CMM Ax module, which places compute hardware directly inside the memory silicon. This setup reduces server power consumption by processing long context text internally without moving data across the motherboard.
Physical hardware displays centered on high capacity modules for server infrastructure, including 256GB 3DS RDIMM, 192GB SOCAMM2, and liquid cooled enterprise SSD units. For maximum bandwidth needs, SK hynix displayed HBM4 hardware mounted to models of NVIDIA Vera Rubin superchips. The company also introduced HBF, a high bandwidth flash design using vertical silicon vias to combine high storage capacity with rapid data transfer speeds for large AI models.
